Microchip Technology Inc. ATSAMD20G16 2024.06.03 Microchip ATSAMD20G16 device: Cortex-M0+ Microcontroller with 64KB Flash, 8KB SRAM, 48-pin package CM0+ r0p1 little 2 false 8 32 AC Analog Comparators AC 0x0 0x0 0x40 registers n AC 22 COMPCTRL0 Comparator Control n 0x20 32 read-write n 0x0 0x0 ENABLE Enable 0 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYST Hysteresis Enable 19 1 INTSEL Interrupt Selection 5 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 2 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 OUT Output 16 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 SINGLE Single-Shot Mode 1 1 SPEED Speed Selection 2 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x1 SWAP Swap Inputs and Invert 15 1 COMPCTRL1 Comparator Control n 0x34 32 read-write n 0x0 0x0 ENABLE Enable 0 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYST Hysteresis Enable 19 1 INTSEL Interrupt Selection 5 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 2 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 OUT Output 16 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 SINGLE Single-Shot Mode 1 1 SPEED Speed Selection 2 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x1 SWAP Swap Inputs and Invert 15 1 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 LPMUX Low-Power Mux 7 1 RUNSTDBY Run in Standby 2 1 SWRST Software Reset 0 1 write-only CTRLB Control B 0x1 8 write-only n 0x0 0x0 START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 EVCTRL Event Control 0x2 16 read-write n 0x0 0x0 COMPEI0 Comparator 0 Event Input 8 1 COMPEI1 Comparator 1 Event Input 9 1 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 WINEO0 Window 0 Event Output Enable 4 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 WIN0 Window 0 4 1 SCALER0 Scaler n 0x40 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 SCALER1 Scaler n 0x61 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 STATUSA Status A 0x8 8 read-only n 0x0 0x0 STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 STATUSB Status B 0x9 8 read-only n 0x0 0x0 READY0 Comparator 0 Ready 0 1 read-only READY1 Comparator 1 Ready 1 1 read-only SYNCBUSY Synchronization Busy 7 1 STATUSC Status C 0xA 8 read-only n 0x0 0x0 STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 WINCTRL Window Control 0xC 8 read-write n 0x0 0x0 WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0x0 INSIDE Interrupt on signal inside window 0x1 BELOW Interrupt on signal below window 0x2 OUTSIDE Interrupt on signal outside window 0x3 ADC Analog Digital Converter ADC 0x0 0x0 0x2C registers n ADC 21 AVGCTRL Average Control 0x2 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xa CALIB Calibration 0x28 16 read-write n 0x0 0x0 BIAS_CAL Bias Calibration Value 8 3 LINEARITY_CAL Linearity Calibration Value 0 8 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run in Standby 2 1 SWRST Software Reset 0 1 CTRLB Control B 0x4 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enabled 3 1 DIFFMODE Differential Mode 0 1 FREERUN Free Running Mode 2 1 LEFTADJ Left Adjusted Result 1 1 PRESCALER Prescaler Configuration 8 3 PRESCALERSelect DIV4 Peripheral clock divided by 4 0x0 DIV8 Peripheral clock divided by 8 0x1 DIV16 Peripheral clock divided by 16 0x2 DIV32 Peripheral clock divided by 32 0x3 DIV64 Peripheral clock divided by 64 0x4 DIV128 Peripheral clock divided by 128 0x5 DIV256 Peripheral clock divided by 256 0x6 DIV512 Peripheral clock divided by 512 0x7 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 DBGCTRL Debug Control 0x2A 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x14 8 read-write n 0x0 0x0 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event In 0 1 SYNCEI Synchronization Event In 1 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x24 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 INPUTCTRL Inputs Control 0x10 32 read-write n 0x0 0x0 GAIN Gain Factor Selection 24 4 GAINSelect 1X 1x 0x0 2X 2x 0x1 4X 4x 0x2 8X 8x 0x3 16X 16x 0x4 DIV2 1/2x 0xf INPUTOFFSET Positive MUX Setting Offset 20 4 INPUTSCAN Number of Input Channels Included in Scan 16 4 MUXNEG Negative MUX Input Selection 8 5 MUXNEGSelect PIN0 ADC AIN0 Pin 0x0 PIN1 ADC AIN1 Pin 0x1 GND Internal ground 0x18 IOGND IO ground 0x19 PIN2 ADC AIN2 Pin 0x2 PIN3 ADC AIN3 Pin 0x3 PIN4 ADC AIN4 Pin 0x4 PIN5 ADC AIN5 Pin 0x5 PIN6 ADC AIN6 Pin 0x6 PIN7 ADC AIN7 Pin 0x7 MUXPOS Positive MUX Input Selection 0 5 MUXPOSSelect PIN0 ADC AIN0 Pin 0x0 PIN1 ADC AIN1 Pin 0x1 PIN16 ADC AIN16 Pin 0x10 PIN17 ADC AIN17 Pin 0x11 PIN18 ADC AIN18 Pin 0x12 PIN19 ADC AIN19 Pin 0x13 TEMP Temperature Reference 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1a SCALEDIOVCC 1/4 Scaled I/O Supply 0x1b DAC DAC Output 0x1c PIN2 ADC AIN2 Pin 0x2 PIN3 ADC AIN3 Pin 0x3 PIN4 ADC AIN4 Pin 0x4 PIN5 ADC AIN5 Pin 0x5 PIN6 ADC AIN6 Pin 0x6 PIN7 ADC AIN7 Pin 0x7 PIN8 ADC AIN8 Pin 0x8 PIN9 ADC AIN9 Pin 0x9 PIN10 ADC AIN10 Pin 0xa PIN11 ADC AIN11 Pin 0xb PIN12 ADC AIN12 Pin 0xc PIN13 ADC AIN13 Pin 0xd PIN14 ADC AIN14 Pin 0xe PIN15 ADC AIN15 Pin 0xf INTENCLR Interrupt Enable Clear 0x16 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 WINMON Window Monitor Interrupt Enable 2 1 INTENSET Interrupt Enable Set 0x17 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 OVERRUN Overrun 1 1 RESRDY Result Ready 0 1 SYNCRDY Synchronization Ready 3 1 WINMON Window Monitor 2 1 OFFSETCORR Offset Correction 0x26 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 REFCTRL Reference Control 0x1 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INT1V 1.0V voltage reference 0x0 INTVCC0 1/1.48 VDDANA 0x1 INTVCC1 1/2 VDDANA (only for VDDANA > 2.0V) 0x2 AREFA External reference 0x3 AREFB External reference 0x4 RESULT Result 0x1A 16 read-only n 0x0 0x0 RESULT Result Conversion Value 0 16 read-only SAMPCTRL Sampling Time Control 0x3 8 read-write n 0x0 0x0 SAMPLEN Sampling Time Length 0 6 STATUS Status 0x19 8 read-only n 0x0 0x0 SYNCBUSY Synchronization Busy 7 1 read-only SWTRIG Software Trigger 0xC 8 read-write n 0x0 0x0 FLUSH ADC Conversion Flush 0 1 START ADC Start Conversion 1 1 WINCTRL Window Monitor Control 0x8 8 read-write n 0x0 0x0 WINMODE Window Monitor Mode 0 3 WINMODESelect DISABLE No window mode (default) 0x0 MODE1 Mode 1: RESULT > WINLT 0x1 MODE2 Mode 2: RESULT < WINUT 0x2 MODE3 Mode 3: WINLT < RESULT < WINUT 0x3 MODE4 Mode 4: !(WINLT < RESULT < WINUT) 0x4 WINLT Window Monitor Lower Threshold 0x1C 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x20 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 DAC Digital Analog Converter DAC 0x0 0x0 0x10 registers n DAC 23 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run in Standby 2 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 read-write n 0x0 0x0 EOEN External Output Enable 0 1 IOEN Internal Output Enable 1 1 LEFTADJ Left Adjusted Data 2 1 REFSEL Reference Selection 6 2 REFSELSelect INT1V Internal 1.0V reference 0x0 AVCC AVCC 0x1 VREFP External reference 0x2 VPD Voltage Pump Disable 3 1 DATA Data 0x8 16 read-write n 0x0 0x0 DATA Data to be converted 0 16 DATABUF Data Buffer 0xC 16 read-write n 0x0 0x0 DATABUF Data Buffer 0 16 EVCTRL Event Control 0x2 8 read-write n 0x0 0x0 EMPTYEO Data Buffer Empty Event Output 1 1 STARTEI Start Conversion Event Input 0 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EMPTY Data Buffer Empty Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 2 1 UNDERRUN Underrun Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EMPTY Data Buffer Empty Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 2 1 UNDERRUN Underrun Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EMPTY Data Buffer Empty 1 1 SYNCRDY Synchronization Ready 2 1 UNDERRUN Underrun 0 1 STATUS Status 0x7 8 read-only n 0x0 0x0 SYNCBUSY Synchronization Busy Status 7 1 read-only DSU Device Service Unit DSU 0x0 0x0 0x2000 registers n ADDR Address 0x4 32 read-write n 0x0 0x0 ADDR Address 2 30 AMOD Access Mode 0 2 CID0 Component Identification 0 0x1FF0 32 read-only n 0x0 0x0 PREAMBLEB0 Preamble Byte 0 0 8 read-only CID1 Component Identification 1 0x1FF4 32 read-only n 0x0 0x0 CCLASS Component Class 4 4 read-only PREAMBLE Preamble 0 4 read-only CID2 Component Identification 2 0x1FF8 32 read-only n 0x0 0x0 PREAMBLEB2 Preamble Byte 2 0 8 read-only CID3 Component Identification 3 0x1FFC 32 read-only n 0x0 0x0 PREAMBLEB3 Preamble Byte 3 0 8 CTRL Control 0x0 8 write-only n 0x0 0x0 ARR Auxiliary Row Read 6 1 write-only CE Chip-Erase 4 1 write-only CRC 32-bit Cyclic Redundancy Code 2 1 write-only MBIST Memory built-in self-test 3 1 write-only SMSA Start Memory Stream Access 7 1 write-only SWRST Software Reset 0 1 write-only DATA Data 0xC 32 read-write n 0x0 0x0 DATA Data 0 32 DCC0 Debug Communication Channel n 0x20 32 read-write n 0x0 0x0 DATA Data 0 32 DCC1 Debug Communication Channel n 0x34 32 read-write n 0x0 0x0 DATA Data 0 32 DCFG0 Device Configuration 0x1E0 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DCFG1 Device Configuration 0x2D4 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DID Device Identification 0x18 32 read-only n 0x0 0x0 DEVSEL Device Select 0 8 read-only DIE Die Number 12 4 read-only FAMILY Family 23 5 read-only FAMILYSelect 0 General purpose microcontroller 0x0 1 PicoPower 0x1 PROCESSOR Processor 28 4 read-only PROCESSORSelect 0 Cortex-M0 0x0 1 Cortex-M0+ 0x1 2 Cortex-M3 0x2 3 Cortex-M4 0x3 REVISION Revision Number 8 4 read-only SERIES Series 16 6 read-only SERIESSelect 0 Cortex-M0+ processor, basic feature set 0x0 1 Cortex-M0+ processor, USB 0x1 END Coresight ROM Table End 0x1008 32 read-only n 0x0 0x0 END End Marker 0 32 ENTRY0 Coresight ROM Table Entry n 0x2000 32 read-only n 0x0 0x0 ADDOFF Address Offset 12 20 read-only EPRES Entry Present 0 1 FMT Format 1 1 read-only ENTRY1 Coresight ROM Table Entry n 0x3004 32 read-only n 0x0 0x0 ADDOFF Address Offset 12 20 read-only EPRES Entry Present 0 1 FMT Format 1 1 read-only LENGTH Length 0x8 32 read-write n 0x0 0x0 LENGTH Length 2 30 MEMTYPE Coresight ROM Table Memory Type 0x1FCC 32 read-only n 0x0 0x0 SMEMP System Memory Present 0 1 PID0 Peripheral Identification 0 0x1FE0 32 read-only n 0x0 0x0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only n 0x0 0x0 JEPIDCL Low part of the JEP-106 Identity Code 4 4 read-only PARTNBH Part Number High 0 4 PID2 Peripheral Identification 2 0x1FE8 32 read-only n 0x0 0x0 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 read-only REVISION Revision Number 4 4 read-only PID3 Peripheral Identification 3 0x1FEC 32 read-only n 0x0 0x0 CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 read-only PID4 Peripheral Identification 4 0x1FD0 32 read-only n 0x0 0x0 FKBC 4KB count 4 4 read-only JEPCC JEP-106 Continuation Code 0 4 PID5 Peripheral Identification 5 0x1FD4 32 read-only n 0x0 0x0 PID6 Peripheral Identification 6 0x1FD8 32 read-only n 0x0 0x0 PID7 Peripheral Identification 7 0x1FDC 32 read-only n 0x0 0x0 STATUSA Status A 0x1 8 read-write n 0x0 0x0 BERR Bus Error 2 1 CRSTEXT CPU Reset Phase Extension 1 1 DONE Done 0 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x2 8 read-only n 0x0 0x0 DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 PROT Protected 0 1 EIC External Interrupt Controller EIC 0x0 0x0 0x40 registers n EIC 4 CONFIG0 Configuration n 0x30 32 read-write n 0x0 0x0 FILTEN0 Filter 0 Enable 3 1 FILTEN1 Filter 1 Enable 7 1 FILTEN2 Filter 2 Enable 11 1 FILTEN3 Filter 3 Enable 15 1 FILTEN4 Filter 4 Enable 19 1 FILTEN5 Filter 5 Enable 23 1 FILTEN6 Filter 6 Enable 27 1 FILTEN7 Filter 7 Enable 31 1 SENSE0 Input Sense 0 Configuration 0 3 SENSE0Select NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 SENSE1 Input Sense 1 Configuration 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE2 Input Sense 2 Configuration 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE3 Input Sense 3 Configuration 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE4 Input Sense 4 Configuration 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE5 Input Sense 5 Configuration 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE6 Input Sense 6 Configuration 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE7 Input Sense 7 Configuration 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 CONFIG1 Configuration n 0x4C 32 read-write n 0x0 0x0 FILTEN0 Filter 0 Enable 3 1 FILTEN1 Filter 1 Enable 7 1 FILTEN2 Filter 2 Enable 11 1 FILTEN3 Filter 3 Enable 15 1 FILTEN4 Filter 4 Enable 19 1 FILTEN5 Filter 5 Enable 23 1 FILTEN6 Filter 6 Enable 27 1 FILTEN7 Filter 7 Enable 31 1 SENSE0 Input Sense 0 Configuration 0 3 SENSE0Select NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 SENSE1 Input Sense 1 Configuration 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE2 Input Sense 2 Configuration 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE3 Input Sense 3 Configuration 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE4 Input Sense 4 Configuration 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE5 Input Sense 5 Configuration 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE6 Input Sense 6 Configuration 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE7 Input Sense 7 Configuration 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 CTRL Control 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 EVCTRL Event Control 0x4 32 read-write n 0x0 0x0 EXTINTEO0 External Interrupt 0 Event Output Enable 0 1 EXTINTEO1 External Interrupt 1 Event Output Enable 1 1 EXTINTEO10 External Interrupt 10 Event Output Enable 10 1 EXTINTEO11 External Interrupt 11 Event Output Enable 11 1 EXTINTEO12 External Interrupt 12 Event Output Enable 12 1 EXTINTEO13 External Interrupt 13 Event Output Enable 13 1 EXTINTEO14 External Interrupt 14 Event Output Enable 14 1 EXTINTEO15 External Interrupt 15 Event Output Enable 15 1 EXTINTEO2 External Interrupt 2 Event Output Enable 2 1 EXTINTEO3 External Interrupt 3 Event Output Enable 3 1 EXTINTEO4 External Interrupt 4 Event Output Enable 4 1 EXTINTEO5 External Interrupt 5 Event Output Enable 5 1 EXTINTEO6 External Interrupt 6 Event Output Enable 6 1 EXTINTEO7 External Interrupt 7 Event Output Enable 7 1 EXTINTEO8 External Interrupt 8 Event Output Enable 8 1 EXTINTEO9 External Interrupt 9 Event Output Enable 9 1 INTENCLR Interrupt Enable Clear 0x8 32 read-write n 0x0 0x0 EXTINT0 External Interrupt 0 Enable 0 1 EXTINT1 External Interrupt 1 Enable 1 1 EXTINT10 External Interrupt 10 Enable 10 1 EXTINT11 External Interrupt 11 Enable 11 1 EXTINT12 External Interrupt 12 Enable 12 1 EXTINT13 External Interrupt 13 Enable 13 1 EXTINT14 External Interrupt 14 Enable 14 1 EXTINT15 External Interrupt 15 Enable 15 1 EXTINT2 External Interrupt 2 Enable 2 1 EXTINT3 External Interrupt 3 Enable 3 1 EXTINT4 External Interrupt 4 Enable 4 1 EXTINT5 External Interrupt 5 Enable 5 1 EXTINT6 External Interrupt 6 Enable 6 1 EXTINT7 External Interrupt 7 Enable 7 1 EXTINT8 External Interrupt 8 Enable 8 1 EXTINT9 External Interrupt 9 Enable 9 1 INTENSET Interrupt Enable Set 0xC 32 read-write n 0x0 0x0 EXTINT0 External Interrupt 0 Enable 0 1 EXTINT1 External Interrupt 1 Enable 1 1 EXTINT10 External Interrupt 10 Enable 10 1 EXTINT11 External Interrupt 11 Enable 11 1 EXTINT12 External Interrupt 12 Enable 12 1 EXTINT13 External Interrupt 13 Enable 13 1 EXTINT14 External Interrupt 14 Enable 14 1 EXTINT15 External Interrupt 15 Enable 15 1 EXTINT2 External Interrupt 2 Enable 2 1 EXTINT3 External Interrupt 3 Enable 3 1 EXTINT4 External Interrupt 4 Enable 4 1 EXTINT5 External Interrupt 5 Enable 5 1 EXTINT6 External Interrupt 6 Enable 6 1 EXTINT7 External Interrupt 7 Enable 7 1 EXTINT8 External Interrupt 8 Enable 8 1 EXTINT9 External Interrupt 9 Enable 9 1 INTFLAG Interrupt Flag Status and Clear 0x10 32 read-write n 0x0 0x0 EXTINT0 External Interrupt 0 0 1 EXTINT1 External Interrupt 1 1 1 EXTINT10 External Interrupt 10 10 1 EXTINT11 External Interrupt 11 11 1 EXTINT12 External Interrupt 12 12 1 EXTINT13 External Interrupt 13 13 1 EXTINT14 External Interrupt 14 14 1 EXTINT15 External Interrupt 15 15 1 EXTINT2 External Interrupt 2 2 1 EXTINT3 External Interrupt 3 3 1 EXTINT4 External Interrupt 4 4 1 EXTINT5 External Interrupt 5 5 1 EXTINT6 External Interrupt 6 6 1 EXTINT7 External Interrupt 7 7 1 EXTINT8 External Interrupt 8 8 1 EXTINT9 External Interrupt 9 9 1 NMICTRL Non-Maskable Interrupt Control 0x2 8 read-write n 0x0 0x0 NMIFILTEN Non-Maskable Interrupt Filter Enable 3 1 NMISENSE Non-Maskable Interrupt Sense 0 3 NMISENSESelect NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 NMIFLAG Non-Maskable Interrupt Flag Status and Clear 0x3 8 read-write n 0x0 0x0 NMI Non-Maskable Interrupt 0 1 STATUS Status 0x1 8 read-only n 0x0 0x0 SYNCBUSY Synchronization Busy 7 1 read-only WAKEUP Wake-Up Enable 0x14 32 read-write n 0x0 0x0 WAKEUPEN0 External Interrupt 0 Wake-up Enable 0 1 WAKEUPEN1 External Interrupt 1 Wake-up Enable 1 1 WAKEUPEN10 External Interrupt 10 Wake-up Enable 10 1 WAKEUPEN11 External Interrupt 11 Wake-up Enable 11 1 WAKEUPEN12 External Interrupt 12 Wake-up Enable 12 1 WAKEUPEN13 External Interrupt 13 Wake-up Enable 13 1 WAKEUPEN14 External Interrupt 14 Wake-up Enable 14 1 WAKEUPEN15 External Interrupt 15 Wake-up Enable 15 1 WAKEUPEN2 External Interrupt 2 Wake-up Enable 2 1 WAKEUPEN3 External Interrupt 3 Wake-up Enable 3 1 WAKEUPEN4 External Interrupt 4 Wake-up Enable 4 1 WAKEUPEN5 External Interrupt 5 Wake-up Enable 5 1 WAKEUPEN6 External Interrupt 6 Wake-up Enable 6 1 WAKEUPEN7 External Interrupt 7 Wake-up Enable 7 1 WAKEUPEN8 External Interrupt 8 Wake-up Enable 8 1 WAKEUPEN9 External Interrupt 9 Wake-up Enable 9 1 EVSYS Event System Interface EVSYS 0x0 0x0 0x2C registers n EVSYS 6 CHANNEL Channel 0x4 32 read-write n 0x0 0x0 CHANNEL Channel Selection 0 3 EDGSEL Edge Detection Selection 26 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 16 6 PATH Path Selection 24 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 SWEVT Software Event 8 1 CHSTATUS Channel Status 0xC 32 read-only n 0x0 0x0 CHBUSY0 Channel 0 Busy 8 1 read-only CHBUSY1 Channel 1 Busy 9 1 read-only CHBUSY2 Channel 2 Busy 10 1 read-only CHBUSY3 Channel 3 Busy 11 1 read-only CHBUSY4 Channel 4 Busy 12 1 read-only CHBUSY5 Channel 5 Busy 13 1 read-only CHBUSY6 Channel 6 Busy 14 1 read-only CHBUSY7 Channel 7 Busy 15 1 read-only USRRDY0 Channel 0 User Ready 0 1 read-only USRRDY1 Channel 1 User Ready 1 1 read-only USRRDY2 Channel 2 User Ready 2 1 read-only USRRDY3 Channel 3 User Ready 3 1 read-only USRRDY4 Channel 4 User Ready 4 1 read-only USRRDY5 Channel 5 User Ready 5 1 read-only USRRDY6 Channel 6 User Ready 6 1 read-only USRRDY7 Channel 7 User Ready 7 1 read-only CTRL Control 0x0 8 write-only n 0x0 0x0 GCLKREQ Generic Clock Requests 4 1 SWRST Software Reset 0 1 write-only INTENCLR Interrupt Enable Clear 0x10 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection Interrupt Enable 8 1 EVD1 Channel 1 Event Detection Interrupt Enable 9 1 EVD2 Channel 2 Event Detection Interrupt Enable 10 1 EVD3 Channel 3 Event Detection Interrupt Enable 11 1 EVD4 Channel 4 Event Detection Interrupt Enable 12 1 EVD5 Channel 5 Event Detection Interrupt Enable 13 1 EVD6 Channel 6 Event Detection Interrupt Enable 14 1 EVD7 Channel 7 Event Detection Interrupt Enable 15 1 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 INTENSET Interrupt Enable Set 0x14 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection Interrupt Enable 8 1 EVD1 Channel 1 Event Detection Interrupt Enable 9 1 EVD2 Channel 2 Event Detection Interrupt Enable 10 1 EVD3 Channel 3 Event Detection Interrupt Enable 11 1 EVD4 Channel 4 Event Detection Interrupt Enable 12 1 EVD5 Channel 5 Event Detection Interrupt Enable 13 1 EVD6 Channel 6 Event Detection Interrupt Enable 14 1 EVD7 Channel 7 Event Detection Interrupt Enable 15 1 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 INTFLAG Interrupt Flag Status and Clear 0x18 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection 8 1 EVD1 Channel 1 Event Detection 9 1 EVD2 Channel 2 Event Detection 10 1 EVD3 Channel 3 Event Detection 11 1 EVD4 Channel 4 Event Detection 12 1 EVD5 Channel 5 Event Detection 13 1 EVD6 Channel 6 Event Detection 14 1 EVD7 Channel 7 Event Detection 15 1 OVR0 Channel 0 Overrun 0 1 OVR1 Channel 1 Overrun 1 1 OVR2 Channel 2 Overrun 2 1 OVR3 Channel 3 Overrun 3 1 OVR4 Channel 4 Overrun 4 1 OVR5 Channel 5 Overrun 5 1 OVR6 Channel 6 Overrun 6 1 OVR7 Channel 7 Overrun 7 1 USER User Multiplexer 0x8 16 read-write n 0x0 0x0 CHANNEL Channel Event Selection 8 4 USER User Multiplexer Selection 0 4 GCLK Generic Clock Generator GCLK 0x0 0x0 0x10 registers n CLKCTRL Generic Clock Control 0x2 16 read-write n 0x0 0x0 CLKEN Clock Enable 14 1 GEN Generic Clock Generator 8 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 ID Generic Clock Selection ID 0 6 IDSelect DFLL48M DFLL48M Reference 0x0 WDT WDT 0x1 SERCOM3_CORE SERCOM3_CORE 0x10 SERCOM4_CORE SERCOM4_CORE 0x11 SERCOM5_CORE SERCOM5_CORE 0x12 TC0_TC1 TC0,TC1 0x13 TC2_TC3 TC2,TC3 0x14 TC4_TC5 TC4,TC5 0x15 TC6_TC7 TC6,TC7 0x16 ADC ADC 0x17 AC_DIG AC_DIG 0x18 AC_ANA AC_ANA 0x19 DAC DAC 0x1a PTC PTC 0x1b RTC RTC 0x2 EIC EIC 0x3 EVSYS_CHANNEL_0 EVSYS_CHANNEL_0 0x4 EVSYS_CHANNEL_1 EVSYS_CHANNEL_1 0x5 EVSYS_CHANNEL_2 EVSYS_CHANNEL_2 0x6 EVSYS_CHANNEL_3 EVSYS_CHANNEL_3 0x7 EVSYS_CHANNEL_4 EVSYS_CHANNEL_4 0x8 EVSYS_CHANNEL_5 EVSYS_CHANNEL_5 0x9 EVSYS_CHANNEL_6 EVSYS_CHANNEL_6 0xa EVSYS_CHANNEL_7 EVSYS_CHANNEL_7 0xb SERCOMX_SLOW SERCOMx_SLOW 0xc SERCOM0_CORE SERCOM0_CORE 0xd SERCOM1_CORE SERCOM1_CORE 0xe SERCOM2_CORE SERCOM2_CORE 0xf WRTLOCK Write Lock 15 1 CTRL Control 0x0 8 read-write n 0x0 0x0 SWRST Software Reset 0 1 GENCTRL Generic Clock Generator Control 0x4 32 read-write n 0x0 0x0 DIVSEL Divide Selection 20 1 GENEN Generic Clock Generator Enable 16 1 ID Generic Clock Generator Selection 0 4 IDSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 IDC Improve Duty Cycle 17 1 OE Output Enable 19 1 OOV Output Off Value 18 1 RUNSTDBY Run in Standby 21 1 SRC Source Select 8 5 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC8M OSC8M oscillator output 0x6 DFLL48M DFLL48M output 0x7 GENDIV Generic Clock Generator Division 0x8 32 read-write n 0x0 0x0 DIV Division Factor 8 16 ID Generic Clock Generator Selection 0 4 IDSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 STATUS Status 0x1 8 read-only n 0x0 0x0 SYNCBUSY Synchronization Busy Status 7 1 read-only NVMCTRL Non-Volatile Memory Controller NVMCTRL 0x0 0x0 0x2C registers n NVMCTRL 5 ADDR Address 0x1C 32 read-write n 0x0 0x0 ADDR NVM Address 0 22 CTRLA Control A 0x0 16 read-write n 0x0 0x0 CMD Command 0 7 CMDSelect ER Erase Row - Erases the row addressed by the ADDR register. 0x2 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x4 LR Lock Region - Locks the region containing the address location in the ADDR register. 0x40 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x41 SPRM Sets the power reduction mode. 0x42 CPRM Clears the power reduction mode. 0x43 PBC Page Buffer Clear - Clears the page buffer. 0x44 SSB Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x45 INVALL Invalidate all cache lines. 0x46 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x5 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x6 SF Security Flow Command 0xa WL Write lockbits 0xf CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xa5 CTRLB Control B 0x4 32 read-write n 0x0 0x0 CACHEDIS Cache Disable 18 1 MANW Manual Write 7 1 READMODE NVMCTRL Read Mode 16 2 READMODESelect NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x0 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. 0x1 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x2 RWS NVM Read Wait States 1 4 RWSSelect SINGLE Single Auto Wait State 0x0 HALF Half Auto Wait State 0x1 DUAL Dual Auto Wait State 0x2 SLEEPPRM Power Reduction Mode during Sleep 8 2 SLEEPPRMSelect WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0x0 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 0x1 DISABLED Auto power reduction disabled. 0x3 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERROR Error Interrupt Enable 1 1 READY NVM Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x10 8 read-write n 0x0 0x0 ERROR Error Interrupt Enable 1 1 READY NVM Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x14 8 read-write n 0x0 0x0 ERROR Error 1 1 READY NVM Ready 0 1 LOCK Lock Section 0x20 16 read-write n 0x0 0x0 LOCK Region Lock Bits 0 16 read-only PARAM NVM Parameter 0x8 32 read-write n 0x0 0x0 NVMP NVM Pages 0 16 read-only PSZ Page Size 16 3 read-only PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 STATUS Status 0x18 16 read-write n 0x0 0x0 LOAD NVM Page Buffer Active Loading 1 1 LOCKE Lock Error Status 3 1 NVME NVM Error 4 1 PRM Power Reduction Mode 0 1 read-only PROGE Programming Error Status 2 1 SB Security Bit Status 8 1 read-only PAC0 Peripheral Access Controller 0 PAC 0x0 0x0 0x8 registers n PAC_WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0x0 WP Write Protection Clear 1 31 PAC_WPSET Write Protection Set 0x4 32 read-write n 0x0 0x0 WP Write Protection Set 1 31 WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0x0 WP Write Protection Clear 1 31 WPSET Write Protection Set 0x4 32 read-write n 0x0 0x0 WP Write Protection Set 1 31 PAC1 Peripheral Access Controller 1 PAC 0x0 0x0 0x8 registers n PAC_WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0x0 WP Write Protection Clear 1 31 PAC_WPSET Write Protection Set 0x4 32 read-write n 0x0 0x0 WP Write Protection Set 1 31 WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0x0 WP Write Protection Clear 1 31 WPSET Write Protection Set 0x4 32 read-write n 0x0 0x0 WP Write Protection Set 1 31 PAC2 Peripheral Access Controller 2 PAC 0x0 0x0 0x8 registers n PAC_WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0x0 WP Write Protection Clear 1 31 PAC_WPSET Write Protection Set 0x4 32 read-write n 0x0 0x0 WP Write Protection Set 1 31 WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0x0 WP Write Protection Clear 1 31 WPSET Write Protection Set 0x4 32 read-write n 0x0 0x0 WP Write Protection Set 1 31 PM Power Manager PM 0x0 0x0 0x2C registers n PM 0 AHBMASK AHB Mask 0x14 32 read-write n 0x0 0x0 DSU_ DSU AHB Clock Mask 3 1 HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 NVMCTRL_ NVMCTRL AHB Clock Mask 4 1 APBAMASK APBA Mask 0x18 32 read-write n 0x0 0x0 EIC_ EIC APB Clock Enable 6 1 GCLK_ GCLK APB Clock Enable 3 1 PAC0_ PAC0 APB Clock Enable 0 1 PM_ PM APB Clock Enable 1 1 RTC_ RTC APB Clock Enable 5 1 SYSCTRL_ SYSCTRL APB Clock Enable 2 1 WDT_ WDT APB Clock Enable 4 1 APBASEL APBA Clock Select 0x9 8 read-write n 0x0 0x0 APBADIV APBA Prescaler Selection 0 3 APBADIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 APBBMASK APBB Mask 0x1C 32 read-write n 0x0 0x0 DSU_ DSU APB Clock Enable 1 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 PAC1_ PAC1 APB Clock Enable 0 1 PORT_ PORT APB Clock Enable 3 1 APBBSEL APBB Clock Select 0xA 8 read-write n 0x0 0x0 APBBDIV APBB Prescaler Selection 0 3 APBBDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 APBCMASK APBC Mask 0x20 32 read-write n 0x0 0x0 AC_ AC APB Clock Enable 17 1 ADC_ ADC APB Clock Enable 16 1 DAC_ DAC APB Clock Enable 18 1 EVSYS_ EVSYS APB Clock Enable 1 1 PAC2_ PAC2 APB Clock Enable 0 1 PTC_ PTC APB Clock Enable 19 1 SERCOM0_ SERCOM0 APB Clock Enable 2 1 SERCOM1_ SERCOM1 APB Clock Enable 3 1 SERCOM2_ SERCOM2 APB Clock Enable 4 1 SERCOM3_ SERCOM3 APB Clock Enable 5 1 SERCOM4_ SERCOM4 APB Clock Enable 6 1 SERCOM5_ SERCOM5 APB Clock Enable 7 1 TC0_ TC0 APB Clock Enable 8 1 TC1_ TC1 APB Clock Enable 9 1 TC2_ TC2 APB Clock Enable 10 1 TC3_ TC3 APB Clock Enable 11 1 TC4_ TC4 APB Clock Enable 12 1 TC5_ TC5 APB Clock Enable 13 1 APBCSEL APBC Clock Select 0xB 8 read-write n 0x0 0x0 APBCDIV APBC Prescaler Selection 0 3 APBCDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 CPUSEL CPU Clock Select 0x8 8 read-write n 0x0 0x0 CPUDIV CPU Prescaler Selection 0 3 CPUDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 CTRL Control 0x0 8 read-write n 0x0 0x0 INTENCLR Interrupt Enable Clear 0x34 8 read-write n 0x0 0x0 CKRDY Clock Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x35 8 read-write n 0x0 0x0 CKRDY Clock Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x36 8 read-write n 0x0 0x0 CKRDY Clock Ready 0 1 RCAUSE Reset Cause 0x38 8 read-only n 0x0 0x0 BOD12 Brown Out 12 Detector Reset 1 1 BOD33 Brown Out 33 Detector Reset 2 1 EXT External Reset 4 1 POR Power On Reset 0 1 SYST System Reset Request 6 1 WDT Watchdog Reset 5 1 SLEEP Sleep Mode 0x1 8 read-write n 0x0 0x0 IDLE Idle Mode Configuration 0 2 IDLESelect CPU The CPU clock domain is stopped 0x0 AHB The CPU and AHB clock domains are stopped 0x1 APB The CPU, AHB and APB clock domains are stopped 0x2 PORT Port Module PORT 0x0 0x0 0x200 registers n CTRL0 Control 0x48 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only CTRL1 Control 0xEC 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only DIR0 Data Direction 0x0 32 read-write n 0x0 0x0 DIR Port Data Direction 0 32 DIR1 Data Direction 0x80 32 read-write n 0x0 0x0 DIR Port Data Direction 0 32 DIRCLR0 Data Direction Clear 0x8 32 read-write n 0x0 0x0 DIRCLR Port Data Direction Clear 0 32 DIRCLR1 Data Direction Clear 0x8C 32 read-write n 0x0 0x0 DIRCLR Port Data Direction Clear 0 32 DIRSET0 Data Direction Set 0x10 32 read-write n 0x0 0x0 DIRSET Port Data Direction Set 0 32 DIRSET1 Data Direction Set 0x98 32 read-write n 0x0 0x0 DIRSET Port Data Direction Set 0 32 DIRTGL0 Data Direction Toggle 0x18 32 read-write n 0x0 0x0 DIRTGL Port Data Direction Toggle 0 32 DIRTGL1 Data Direction Toggle 0xA4 32 read-write n 0x0 0x0 DIRTGL Port Data Direction Toggle 0 32 IN0 Data Input Value 0x40 32 read-only n 0x0 0x0 IN Port Data Input Value 0 32 IN1 Data Input Value 0xE0 32 read-only n 0x0 0x0 IN Port Data Input Value 0 32 OUT0 Data Output Value 0x20 32 read-write n 0x0 0x0 OUT Port Data Output Value 0 32 OUT1 Data Output Value 0xB0 32 read-write n 0x0 0x0 OUT Port Data Output Value 0 32 OUTCLR0 Data Output Value Clear 0x28 32 read-write n 0x0 0x0 OUTCLR Port Data Output Value Clear 0 32 OUTCLR1 Data Output Value Clear 0xBC 32 read-write n 0x0 0x0 OUTCLR Port Data Output Value Clear 0 32 OUTSET0 Data Output Value Set 0x30 32 read-write n 0x0 0x0 OUTSET Port Data Output Value Set 0 32 OUTSET1 Data Output Value Set 0xC8 32 read-write n 0x0 0x0 OUTSET Port Data Output Value Set 0 32 OUTTGL0 Data Output Value Toggle 0x38 32 read-write n 0x0 0x0 OUTTGL Port Data Output Value Toggle 0 32 OUTTGL1 Data Output Value Toggle 0xD4 32 read-write n 0x0 0x0 OUTTGL Port Data Output Value Toggle 0 32 PINCFG0_0 Pin Configuration n - Group 0 0x80 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_1 Pin Configuration n - Group 0 0xC1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_10 Pin Configuration n - Group 0 0x337 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_11 Pin Configuration n - Group 0 0x382 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_12 Pin Configuration n - Group 0 0x3CE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_13 Pin Configuration n - Group 0 0x41B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_14 Pin Configuration n - Group 0 0x469 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_15 Pin Configuration n - Group 0 0x4B8 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_16 Pin Configuration n - Group 0 0x508 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_17 Pin Configuration n - Group 0 0x559 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_18 Pin Configuration n - Group 0 0x5AB 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_19 Pin Configuration n - Group 0 0x5FE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_2 Pin Configuration n - Group 0 0x103 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_20 Pin Configuration n - Group 0 0x652 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_21 Pin Configuration n - Group 0 0x6A7 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_22 Pin Configuration n - Group 0 0x6FD 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_23 Pin Configuration n - Group 0 0x754 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_24 Pin Configuration n - Group 0 0x7AC 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_25 Pin Configuration n - Group 0 0x805 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_26 Pin Configuration n - Group 0 0x85F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_27 Pin Configuration n - Group 0 0x8BA 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_28 Pin Configuration n - Group 0 0x916 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_29 Pin Configuration n - Group 0 0x973 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_3 Pin Configuration n - Group 0 0x146 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_30 Pin Configuration n - Group 0 0x9D1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_31 Pin Configuration n - Group 0 0xA30 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_4 Pin Configuration n - Group 0 0x18A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_5 Pin Configuration n - Group 0 0x1CF 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_6 Pin Configuration n - Group 0 0x215 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_7 Pin Configuration n - Group 0 0x25C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_8 Pin Configuration n - Group 0 0x2A4 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_9 Pin Configuration n - Group 0 0x2ED 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG1_0 Pin Configuration n - Group 1 0x180 read-write n 0x0 0x0 PINCFG1_1 Pin Configuration n - Group 1 0x241 read-write n 0x0 0x0 PINCFG1_10 Pin Configuration n - Group 1 0x937 read-write n 0x0 0x0 PINCFG1_11 Pin Configuration n - Group 1 0xA02 read-write n 0x0 0x0 PINCFG1_12 Pin Configuration n - Group 1 0xACE read-write n 0x0 0x0 PINCFG1_13 Pin Configuration n - Group 1 0xB9B read-write n 0x0 0x0 PINCFG1_14 Pin Configuration n - Group 1 0xC69 read-write n 0x0 0x0 PINCFG1_15 Pin Configuration n - Group 1 0xD38 read-write n 0x0 0x0 PINCFG1_16 Pin Configuration n - Group 1 0xE08 read-write n 0x0 0x0 PINCFG1_17 Pin Configuration n - Group 1 0xED9 read-write n 0x0 0x0 PINCFG1_18 Pin Configuration n - Group 1 0xFAB read-write n 0x0 0x0 PINCFG1_19 Pin Configuration n - Group 1 0x107E read-write n 0x0 0x0 PINCFG1_2 Pin Configuration n - Group 1 0x303 read-write n 0x0 0x0 PINCFG1_20 Pin Configuration n - Group 1 0x1152 read-write n 0x0 0x0 PINCFG1_21 Pin Configuration n - Group 1 0x1227 read-write n 0x0 0x0 PINCFG1_22 Pin Configuration n - Group 1 0x12FD read-write n 0x0 0x0 PINCFG1_23 Pin Configuration n - Group 1 0x13D4 read-write n 0x0 0x0 PINCFG1_24 Pin Configuration n - Group 1 0x14AC read-write n 0x0 0x0 PINCFG1_25 Pin Configuration n - Group 1 0x1585 read-write n 0x0 0x0 PINCFG1_26 Pin Configuration n - Group 1 0x165F read-write n 0x0 0x0 PINCFG1_27 Pin Configuration n - Group 1 0x173A read-write n 0x0 0x0 PINCFG1_28 Pin Configuration n - Group 1 0x1816 read-write n 0x0 0x0 PINCFG1_29 Pin Configuration n - Group 1 0x18F3 read-write n 0x0 0x0 PINCFG1_3 Pin Configuration n - Group 1 0x3C6 read-write n 0x0 0x0 PINCFG1_30 Pin Configuration n - Group 1 0x19D1 read-write n 0x0 0x0 PINCFG1_31 Pin Configuration n - Group 1 0x1AB0 read-write n 0x0 0x0 PINCFG1_4 Pin Configuration n - Group 1 0x48A read-write n 0x0 0x0 PINCFG1_5 Pin Configuration n - Group 1 0x54F read-write n 0x0 0x0 PINCFG1_6 Pin Configuration n - Group 1 0x615 read-write n 0x0 0x0 PINCFG1_7 Pin Configuration n - Group 1 0x6DC read-write n 0x0 0x0 PINCFG1_8 Pin Configuration n - Group 1 0x7A4 read-write n 0x0 0x0 PINCFG1_9 Pin Configuration n - Group 1 0x86D read-write n 0x0 0x0 PMUX0_0 Peripheral Multiplexing n - Group 0 0x60 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_1 Peripheral Multiplexing n - Group 0 0x91 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_10 Peripheral Multiplexing n - Group 0 0x277 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_11 Peripheral Multiplexing n - Group 0 0x2B2 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_12 Peripheral Multiplexing n - Group 0 0x2EE 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_13 Peripheral Multiplexing n - Group 0 0x32B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_14 Peripheral Multiplexing n - Group 0 0x369 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_15 Peripheral Multiplexing n - Group 0 0x3A8 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_2 Peripheral Multiplexing n - Group 0 0xC3 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_3 Peripheral Multiplexing n - Group 0 0xF6 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_4 Peripheral Multiplexing n - Group 0 0x12A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_5 Peripheral Multiplexing n - Group 0 0x15F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_6 Peripheral Multiplexing n - Group 0 0x195 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_7 Peripheral Multiplexing n - Group 0 0x1CC 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_8 Peripheral Multiplexing n - Group 0 0x204 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_9 Peripheral Multiplexing n - Group 0 0x23D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX1_0 Peripheral Multiplexing n - Group 1 0x160 read-write n 0x0 0x0 PMUX1_1 Peripheral Multiplexing n - Group 1 0x211 read-write n 0x0 0x0 PMUX1_10 Peripheral Multiplexing n - Group 1 0x877 read-write n 0x0 0x0 PMUX1_11 Peripheral Multiplexing n - Group 1 0x932 read-write n 0x0 0x0 PMUX1_12 Peripheral Multiplexing n - Group 1 0x9EE read-write n 0x0 0x0 PMUX1_13 Peripheral Multiplexing n - Group 1 0xAAB read-write n 0x0 0x0 PMUX1_14 Peripheral Multiplexing n - Group 1 0xB69 read-write n 0x0 0x0 PMUX1_15 Peripheral Multiplexing n - Group 1 0xC28 read-write n 0x0 0x0 PMUX1_2 Peripheral Multiplexing n - Group 1 0x2C3 read-write n 0x0 0x0 PMUX1_3 Peripheral Multiplexing n - Group 1 0x376 read-write n 0x0 0x0 PMUX1_4 Peripheral Multiplexing n - Group 1 0x42A read-write n 0x0 0x0 PMUX1_5 Peripheral Multiplexing n - Group 1 0x4DF read-write n 0x0 0x0 PMUX1_6 Peripheral Multiplexing n - Group 1 0x595 read-write n 0x0 0x0 PMUX1_7 Peripheral Multiplexing n - Group 1 0x64C read-write n 0x0 0x0 PMUX1_8 Peripheral Multiplexing n - Group 1 0x704 read-write n 0x0 0x0 PMUX1_9 Peripheral Multiplexing n - Group 1 0x7BD read-write n 0x0 0x0 WRCONFIG0 Write Configuration 0x50 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 WRCONFIG1 Write Configuration 0xF8 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 PORT_IOBUS Port Module (IOBUS) PORT 0x0 0x0 0x200 registers n CTRL0 Control 0x48 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only CTRL1 Control 0xEC 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only DIR0 Data Direction 0x0 32 read-write n 0x0 0x0 DIR Port Data Direction 0 32 DIR1 Data Direction 0x80 32 read-write n 0x0 0x0 DIR Port Data Direction 0 32 DIRCLR0 Data Direction Clear 0x8 32 read-write n 0x0 0x0 DIRCLR Port Data Direction Clear 0 32 DIRCLR1 Data Direction Clear 0x8C 32 read-write n 0x0 0x0 DIRCLR Port Data Direction Clear 0 32 DIRSET0 Data Direction Set 0x10 32 read-write n 0x0 0x0 DIRSET Port Data Direction Set 0 32 DIRSET1 Data Direction Set 0x98 32 read-write n 0x0 0x0 DIRSET Port Data Direction Set 0 32 DIRTGL0 Data Direction Toggle 0x18 32 read-write n 0x0 0x0 DIRTGL Port Data Direction Toggle 0 32 DIRTGL1 Data Direction Toggle 0xA4 32 read-write n 0x0 0x0 DIRTGL Port Data Direction Toggle 0 32 IN0 Data Input Value 0x40 32 read-only n 0x0 0x0 IN Port Data Input Value 0 32 IN1 Data Input Value 0xE0 32 read-only n 0x0 0x0 IN Port Data Input Value 0 32 OUT0 Data Output Value 0x20 32 read-write n 0x0 0x0 OUT Port Data Output Value 0 32 OUT1 Data Output Value 0xB0 32 read-write n 0x0 0x0 OUT Port Data Output Value 0 32 OUTCLR0 Data Output Value Clear 0x28 32 read-write n 0x0 0x0 OUTCLR Port Data Output Value Clear 0 32 OUTCLR1 Data Output Value Clear 0xBC 32 read-write n 0x0 0x0 OUTCLR Port Data Output Value Clear 0 32 OUTSET0 Data Output Value Set 0x30 32 read-write n 0x0 0x0 OUTSET Port Data Output Value Set 0 32 OUTSET1 Data Output Value Set 0xC8 32 read-write n 0x0 0x0 OUTSET Port Data Output Value Set 0 32 OUTTGL0 Data Output Value Toggle 0x38 32 read-write n 0x0 0x0 OUTTGL Port Data Output Value Toggle 0 32 OUTTGL1 Data Output Value Toggle 0xD4 32 read-write n 0x0 0x0 OUTTGL Port Data Output Value Toggle 0 32 PINCFG0_0 Pin Configuration n - Group 0 0x80 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_1 Pin Configuration n - Group 0 0xC1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_10 Pin Configuration n - Group 0 0x337 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_11 Pin Configuration n - Group 0 0x382 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_12 Pin Configuration n - Group 0 0x3CE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_13 Pin Configuration n - Group 0 0x41B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_14 Pin Configuration n - Group 0 0x469 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_15 Pin Configuration n - Group 0 0x4B8 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_16 Pin Configuration n - Group 0 0x508 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_17 Pin Configuration n - Group 0 0x559 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_18 Pin Configuration n - Group 0 0x5AB 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_19 Pin Configuration n - Group 0 0x5FE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_2 Pin Configuration n - Group 0 0x103 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_20 Pin Configuration n - Group 0 0x652 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_21 Pin Configuration n - Group 0 0x6A7 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_22 Pin Configuration n - Group 0 0x6FD 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_23 Pin Configuration n - Group 0 0x754 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_24 Pin Configuration n - Group 0 0x7AC 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_25 Pin Configuration n - Group 0 0x805 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_26 Pin Configuration n - Group 0 0x85F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_27 Pin Configuration n - Group 0 0x8BA 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_28 Pin Configuration n - Group 0 0x916 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_29 Pin Configuration n - Group 0 0x973 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_3 Pin Configuration n - Group 0 0x146 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_30 Pin Configuration n - Group 0 0x9D1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_31 Pin Configuration n - Group 0 0xA30 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_4 Pin Configuration n - Group 0 0x18A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_5 Pin Configuration n - Group 0 0x1CF 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_6 Pin Configuration n - Group 0 0x215 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_7 Pin Configuration n - Group 0 0x25C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_8 Pin Configuration n - Group 0 0x2A4 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_9 Pin Configuration n - Group 0 0x2ED 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG1_0 Pin Configuration n - Group 1 0x180 read-write n 0x0 0x0 PINCFG1_1 Pin Configuration n - Group 1 0x241 read-write n 0x0 0x0 PINCFG1_10 Pin Configuration n - Group 1 0x937 read-write n 0x0 0x0 PINCFG1_11 Pin Configuration n - Group 1 0xA02 read-write n 0x0 0x0 PINCFG1_12 Pin Configuration n - Group 1 0xACE read-write n 0x0 0x0 PINCFG1_13 Pin Configuration n - Group 1 0xB9B read-write n 0x0 0x0 PINCFG1_14 Pin Configuration n - Group 1 0xC69 read-write n 0x0 0x0 PINCFG1_15 Pin Configuration n - Group 1 0xD38 read-write n 0x0 0x0 PINCFG1_16 Pin Configuration n - Group 1 0xE08 read-write n 0x0 0x0 PINCFG1_17 Pin Configuration n - Group 1 0xED9 read-write n 0x0 0x0 PINCFG1_18 Pin Configuration n - Group 1 0xFAB read-write n 0x0 0x0 PINCFG1_19 Pin Configuration n - Group 1 0x107E read-write n 0x0 0x0 PINCFG1_2 Pin Configuration n - Group 1 0x303 read-write n 0x0 0x0 PINCFG1_20 Pin Configuration n - Group 1 0x1152 read-write n 0x0 0x0 PINCFG1_21 Pin Configuration n - Group 1 0x1227 read-write n 0x0 0x0 PINCFG1_22 Pin Configuration n - Group 1 0x12FD read-write n 0x0 0x0 PINCFG1_23 Pin Configuration n - Group 1 0x13D4 read-write n 0x0 0x0 PINCFG1_24 Pin Configuration n - Group 1 0x14AC read-write n 0x0 0x0 PINCFG1_25 Pin Configuration n - Group 1 0x1585 read-write n 0x0 0x0 PINCFG1_26 Pin Configuration n - Group 1 0x165F read-write n 0x0 0x0 PINCFG1_27 Pin Configuration n - Group 1 0x173A read-write n 0x0 0x0 PINCFG1_28 Pin Configuration n - Group 1 0x1816 read-write n 0x0 0x0 PINCFG1_29 Pin Configuration n - Group 1 0x18F3 read-write n 0x0 0x0 PINCFG1_3 Pin Configuration n - Group 1 0x3C6 read-write n 0x0 0x0 PINCFG1_30 Pin Configuration n - Group 1 0x19D1 read-write n 0x0 0x0 PINCFG1_31 Pin Configuration n - Group 1 0x1AB0 read-write n 0x0 0x0 PINCFG1_4 Pin Configuration n - Group 1 0x48A read-write n 0x0 0x0 PINCFG1_5 Pin Configuration n - Group 1 0x54F read-write n 0x0 0x0 PINCFG1_6 Pin Configuration n - Group 1 0x615 read-write n 0x0 0x0 PINCFG1_7 Pin Configuration n - Group 1 0x6DC read-write n 0x0 0x0 PINCFG1_8 Pin Configuration n - Group 1 0x7A4 read-write n 0x0 0x0 PINCFG1_9 Pin Configuration n - Group 1 0x86D read-write n 0x0 0x0 PMUX0_0 Peripheral Multiplexing n - Group 0 0x60 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_1 Peripheral Multiplexing n - Group 0 0x91 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_10 Peripheral Multiplexing n - Group 0 0x277 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_11 Peripheral Multiplexing n - Group 0 0x2B2 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_12 Peripheral Multiplexing n - Group 0 0x2EE 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_13 Peripheral Multiplexing n - Group 0 0x32B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_14 Peripheral Multiplexing n - Group 0 0x369 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_15 Peripheral Multiplexing n - Group 0 0x3A8 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_2 Peripheral Multiplexing n - Group 0 0xC3 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_3 Peripheral Multiplexing n - Group 0 0xF6 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_4 Peripheral Multiplexing n - Group 0 0x12A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_5 Peripheral Multiplexing n - Group 0 0x15F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_6 Peripheral Multiplexing n - Group 0 0x195 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_7 Peripheral Multiplexing n - Group 0 0x1CC 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_8 Peripheral Multiplexing n - Group 0 0x204 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_9 Peripheral Multiplexing n - Group 0 0x23D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX1_0 Peripheral Multiplexing n - Group 1 0x160 read-write n 0x0 0x0 PMUX1_1 Peripheral Multiplexing n - Group 1 0x211 read-write n 0x0 0x0 PMUX1_10 Peripheral Multiplexing n - Group 1 0x877 read-write n 0x0 0x0 PMUX1_11 Peripheral Multiplexing n - Group 1 0x932 read-write n 0x0 0x0 PMUX1_12 Peripheral Multiplexing n - Group 1 0x9EE read-write n 0x0 0x0 PMUX1_13 Peripheral Multiplexing n - Group 1 0xAAB read-write n 0x0 0x0 PMUX1_14 Peripheral Multiplexing n - Group 1 0xB69 read-write n 0x0 0x0 PMUX1_15 Peripheral Multiplexing n - Group 1 0xC28 read-write n 0x0 0x0 PMUX1_2 Peripheral Multiplexing n - Group 1 0x2C3 read-write n 0x0 0x0 PMUX1_3 Peripheral Multiplexing n - Group 1 0x376 read-write n 0x0 0x0 PMUX1_4 Peripheral Multiplexing n - Group 1 0x42A read-write n 0x0 0x0 PMUX1_5 Peripheral Multiplexing n - Group 1 0x4DF read-write n 0x0 0x0 PMUX1_6 Peripheral Multiplexing n - Group 1 0x595 read-write n 0x0 0x0 PMUX1_7 Peripheral Multiplexing n - Group 1 0x64C read-write n 0x0 0x0 PMUX1_8 Peripheral Multiplexing n - Group 1 0x704 read-write n 0x0 0x0 PMUX1_9 Peripheral Multiplexing n - Group 1 0x7BD read-write n 0x0 0x0 WRCONFIG0 Write Configuration 0x50 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 WRCONFIG1 Write Configuration 0xF8 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 RTC Real-Time Counter RTC 0x0 0x0 0x40 registers n RTC 3 ALARM1 MODE2 Alarm n Value 0x18 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0x0 PM Afternoon hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 CLOCK MODE2 Clock Value 0x10 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x0 PM Afternoon Hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 COMP0 MODE1 Compare n Value 0x18 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COMP1 MODE0 Compare n Value 0x18 32 read-write n 0x0 0x0 COMP Compare Value 0 16 COUNT MODE0 Counter Value 0x10 32 read-write n 0x0 0x0 COUNT Counter Value 0 16 CTRL MODE1 Control 0x0 16 read-write n 0x0 0x0 CLKREP Clock Representation 6 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa SWRST Software Reset 0 1 write-only DBGCTRL Debug Control 0xB 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 EVCTRL MODE1 Event Control 0x4 16 read-write n 0x0 0x0 ALARMEO0 Alarm 0 Event Output Enable 8 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 FREQCORR Frequency Correction 0xC 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 INTENCLR MODE1 Interrupt Enable Clear 0x6 8 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 0 1 CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 INTENSET MODE1 Interrupt Enable Set 0x7 8 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 0 1 CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 INTFLAG MODE1 Interrupt Flag Status and Clear 0x8 8 read-write n 0x0 0x0 ALARM0 Alarm 0 0 1 CMP0 Compare 0 0 1 CMP1 Compare 1 1 1 OVF Overflow 7 1 SYNCRDY Synchronization Ready 6 1 MASK1 MODE2 Alarm n Mask 0x1C 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE0 - COMP0 32-bit Counter with Single 32-bit Compare - - MODE0 Compare n Value 0x30 32 read-write n 0x0 0x0 COMP Compare Value 0 32 MODE0 - COUNT 32-bit Counter with Single 32-bit Compare - - MODE0 Counter Value 0x10 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 MODE0 - CTRL 32-bit Counter with Single 32-bit Compare - - MODE0 Control 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa SWRST Software Reset 0 1 write-only MODE0 - DBGCTRL 32-bit Counter with Single 32-bit Compare - - Debug Control 0xB 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE0 - EVCTRL 32-bit Counter with Single 32-bit Compare - - MODE0 Event Control 0x4 16 read-write n 0x0 0x0 CMPEO0 Compare 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE0 - FREQCORR 32-bit Counter with Single 32-bit Compare - - Frequency Correction 0xC 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE0 - INTENCLR 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Clear 0x6 8 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 0 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE0 - INTENSET 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Set 0x7 8 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 0 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE0 - INTFLAG 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Flag Status and Clear 0x8 8 read-write n 0x0 0x0 CMP0 Compare 0 0 1 OVF Overflow 7 1 SYNCRDY Synchronization Ready 6 1 MODE0 - READREQ 32-bit Counter with Single 32-bit Compare - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only MODE0 - STATUS 32-bit Counter with Single 32-bit Compare - - Status 0xA 8 read-write n 0x0 0x0 SYNCBUSY Synchronization Busy 7 1 read-only MODE1 - COMP0 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x30 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COMP1 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x4A 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COUNT 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 MODE1 - CTRL 16-bit Counter with Two 16-bit Compares - - MODE1 Control 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa SWRST Software Reset 0 1 write-only MODE1 - DBGCTRL 16-bit Counter with Two 16-bit Compares - - Debug Control 0xB 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE1 - EVCTRL 16-bit Counter with Two 16-bit Compares - - MODE1 Event Control 0x4 16 read-write n 0x0 0x0 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE1 - FREQCORR 16-bit Counter with Two 16-bit Compares - - Frequency Correction 0xC 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE1 - INTENCLR 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Clear 0x6 8 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE1 - INTENSET 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Set 0x7 8 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE1 - INTFLAG 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Flag Status and Clear 0x8 8 read-write n 0x0 0x0 CMP0 Compare 0 0 1 CMP1 Compare 1 1 1 OVF Overflow 7 1 SYNCRDY Synchronization Ready 6 1 MODE1 - PER 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Period 0x14 16 read-write n 0x0 0x0 PER Counter Period 0 16 MODE1 - READREQ 16-bit Counter with Two 16-bit Compares - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only MODE1 - STATUS 16-bit Counter with Two 16-bit Compares - - Status 0xA 8 read-write n 0x0 0x0 SYNCBUSY Synchronization Busy 7 1 read-only MODE2 - ALARM0 Clock/Calendar with Alarm - - MODE2 Alarm n Value 0x30 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CLOCK Clock/Calendar with Alarm - - MODE2 Clock Value 0x10 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect PM Afternoon Hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CTRL Clock/Calendar with Alarm - - MODE2 Control 0x0 16 read-write n 0x0 0x0 CLKREP Clock Representation 6 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa SWRST Software Reset 0 1 write-only MODE2 - DBGCTRL Clock/Calendar with Alarm - - Debug Control 0xB 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE2 - EVCTRL Clock/Calendar with Alarm - - MODE2 Event Control 0x4 16 read-write n 0x0 0x0 ALARMEO0 Alarm 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE2 - FREQCORR Clock/Calendar with Alarm - - Frequency Correction 0xC 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE2 - INTENCLR Clock/Calendar with Alarm - - MODE2 Interrupt Enable Clear 0x6 8 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 0 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE2 - INTENSET Clock/Calendar with Alarm - - MODE2 Interrupt Enable Set 0x7 8 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 0 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE2 - INTFLAG Clock/Calendar with Alarm - - MODE2 Interrupt Flag Status and Clear 0x8 8 read-write n 0x0 0x0 ALARM0 Alarm 0 0 1 OVF Overflow 7 1 SYNCRDY Synchronization Ready 6 1 MODE2 - MASK0 Clock/Calendar with Alarm - - MODE2 Alarm n Mask 0x38 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE2 - READREQ Clock/Calendar with Alarm - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only MODE2 - STATUS Clock/Calendar with Alarm - - Status 0xA 8 read-write n 0x0 0x0 SYNCBUSY Synchronization Busy 7 1 read-only PER MODE1 Counter Period 0x14 16 read-write n 0x0 0x0 PER Counter Period 0 16 READREQ Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only STATUS Status 0xA 8 read-write n 0x0 0x0 SYNCBUSY Synchronization Busy 7 1 read-only SERCOM0 Serial Communication Interface 0 SERCOM 0x0 0x0 0x20 registers n SERCOM0 7 ADDR I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 BAUD SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Value 0 16 BAUDLOW Master Baud Rate Low 8 8 CTRLA SPI Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 0 USART frame 0x0 1 USART frame with parity 0x1 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 CTRLB SPI Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only PLOADEN Slave Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 TXEN Transmitter Enable 16 1 DATA SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 DBGCTRL SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 INTENCLR SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTENSET SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 DRE Data Register Empty 0 1 read-only MB Master on Bus 0 1 PREC Stop Received 0 1 RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave on Bus 1 1 TXC Transmit Complete 1 1 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x14 8 read-write n 0x0 0x0 ADDR Address 0 8 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xA 16 read-write n 0x0 0x0 BAUD Master Baud Rate 0 8 BAUDLOW Master Baud Rate Low 8 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 MB Master on Bus 0 1 SB Slave on Bus 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 1 7 ADDRMASK Address Mask 17 7 GENCEN General Call Address Enable 0 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 PREC Stop Received 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x10 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Register 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 PLOADEN Slave Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only TXC Transmit Complete 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud 0xA 16 read-write n 0x0 0x0 BAUD Baud Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect 0 USART frame 0x0 1 USART frame with parity 0x1 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete 1 1 SERCOM_USART - STATUS USART Mode - - USART Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 FERR Frame Error 1 1 PERR Parity Error 0 1 SYNCBUSY Synchronization Busy 15 1 read-only STATUS SPI Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only FERR Frame Error 1 1 LOWTOUT SCL Low Time-out 6 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM1 Serial Communication Interface 1 SERCOM 0x0 0x0 0x20 registers n SERCOM1 8 ADDR I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 BAUD SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Value 0 16 BAUDLOW Master Baud Rate Low 8 8 CTRLA SPI Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 0 USART frame 0x0 1 USART frame with parity 0x1 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 CTRLB SPI Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only PLOADEN Slave Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 TXEN Transmitter Enable 16 1 DATA SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 DBGCTRL SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 INTENCLR SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTENSET SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 DRE Data Register Empty 0 1 read-only MB Master on Bus 0 1 PREC Stop Received 0 1 RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave on Bus 1 1 TXC Transmit Complete 1 1 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x14 8 read-write n 0x0 0x0 ADDR Address 0 8 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xA 16 read-write n 0x0 0x0 BAUD Master Baud Rate 0 8 BAUDLOW Master Baud Rate Low 8 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 MB Master on Bus 0 1 SB Slave on Bus 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 1 7 ADDRMASK Address Mask 17 7 GENCEN General Call Address Enable 0 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 PREC Stop Received 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x10 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Register 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 PLOADEN Slave Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only TXC Transmit Complete 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud 0xA 16 read-write n 0x0 0x0 BAUD Baud Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect 0 USART frame 0x0 1 USART frame with parity 0x1 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete 1 1 SERCOM_USART - STATUS USART Mode - - USART Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 FERR Frame Error 1 1 PERR Parity Error 0 1 SYNCBUSY Synchronization Busy 15 1 read-only STATUS SPI Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only FERR Frame Error 1 1 LOWTOUT SCL Low Time-out 6 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM2 Serial Communication Interface 2 SERCOM 0x0 0x0 0x20 registers n SERCOM2 9 ADDR I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 BAUD SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Value 0 16 BAUDLOW Master Baud Rate Low 8 8 CTRLA SPI Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 0 USART frame 0x0 1 USART frame with parity 0x1 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 CTRLB SPI Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only PLOADEN Slave Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 TXEN Transmitter Enable 16 1 DATA SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 DBGCTRL SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 INTENCLR SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTENSET SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 DRE Data Register Empty 0 1 read-only MB Master on Bus 0 1 PREC Stop Received 0 1 RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave on Bus 1 1 TXC Transmit Complete 1 1 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x14 8 read-write n 0x0 0x0 ADDR Address 0 8 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xA 16 read-write n 0x0 0x0 BAUD Master Baud Rate 0 8 BAUDLOW Master Baud Rate Low 8 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 MB Master on Bus 0 1 SB Slave on Bus 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 1 7 ADDRMASK Address Mask 17 7 GENCEN General Call Address Enable 0 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 PREC Stop Received 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x10 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Register 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 PLOADEN Slave Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only TXC Transmit Complete 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud 0xA 16 read-write n 0x0 0x0 BAUD Baud Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect 0 USART frame 0x0 1 USART frame with parity 0x1 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete 1 1 SERCOM_USART - STATUS USART Mode - - USART Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 FERR Frame Error 1 1 PERR Parity Error 0 1 SYNCBUSY Synchronization Busy 15 1 read-only STATUS SPI Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only FERR Frame Error 1 1 LOWTOUT SCL Low Time-out 6 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM3 Serial Communication Interface 3 SERCOM 0x0 0x0 0x20 registers n SERCOM3 10 ADDR I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 BAUD SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Value 0 16 BAUDLOW Master Baud Rate Low 8 8 CTRLA SPI Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 0 USART frame 0x0 1 USART frame with parity 0x1 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 CTRLB SPI Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only PLOADEN Slave Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 TXEN Transmitter Enable 16 1 DATA SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 DBGCTRL SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 INTENCLR SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTENSET SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 DRE Data Register Empty 0 1 read-only MB Master on Bus 0 1 PREC Stop Received 0 1 RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave on Bus 1 1 TXC Transmit Complete 1 1 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x14 8 read-write n 0x0 0x0 ADDR Address 0 8 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xA 16 read-write n 0x0 0x0 BAUD Master Baud Rate 0 8 BAUDLOW Master Baud Rate Low 8 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 MB Master on Bus 0 1 SB Slave on Bus 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 1 7 ADDRMASK Address Mask 17 7 GENCEN General Call Address Enable 0 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 PREC Stop Received 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x10 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Register 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 PLOADEN Slave Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only TXC Transmit Complete 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud 0xA 16 read-write n 0x0 0x0 BAUD Baud Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect 0 USART frame 0x0 1 USART frame with parity 0x1 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete 1 1 SERCOM_USART - STATUS USART Mode - - USART Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 FERR Frame Error 1 1 PERR Parity Error 0 1 SYNCBUSY Synchronization Busy 15 1 read-only STATUS SPI Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only FERR Frame Error 1 1 LOWTOUT SCL Low Time-out 6 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM4 Serial Communication Interface 4 SERCOM 0x0 0x0 0x20 registers n SERCOM4 11 ADDR I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 BAUD SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Value 0 16 BAUDLOW Master Baud Rate Low 8 8 CTRLA SPI Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 0 USART frame 0x0 1 USART frame with parity 0x1 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 CTRLB SPI Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only PLOADEN Slave Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 TXEN Transmitter Enable 16 1 DATA SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 DBGCTRL SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 INTENCLR SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTENSET SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 DRE Data Register Empty 0 1 read-only MB Master on Bus 0 1 PREC Stop Received 0 1 RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave on Bus 1 1 TXC Transmit Complete 1 1 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x14 8 read-write n 0x0 0x0 ADDR Address 0 8 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xA 16 read-write n 0x0 0x0 BAUD Master Baud Rate 0 8 BAUDLOW Master Baud Rate Low 8 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 MB Master on Bus 0 1 SB Slave on Bus 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 1 7 ADDRMASK Address Mask 17 7 GENCEN General Call Address Enable 0 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 PREC Stop Received 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x10 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Register 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 PLOADEN Slave Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only TXC Transmit Complete 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud 0xA 16 read-write n 0x0 0x0 BAUD Baud Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect 0 USART frame 0x0 1 USART frame with parity 0x1 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete 1 1 SERCOM_USART - STATUS USART Mode - - USART Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 FERR Frame Error 1 1 PERR Parity Error 0 1 SYNCBUSY Synchronization Busy 15 1 read-only STATUS SPI Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only FERR Frame Error 1 1 LOWTOUT SCL Low Time-out 6 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM5 Serial Communication Interface 5 SERCOM 0x0 0x0 0x20 registers n SERCOM5 12 ADDR I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 BAUD SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Value 0 16 BAUDLOW Master Baud Rate Low 8 8 CTRLA SPI Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 0 USART frame 0x0 1 USART frame with parity 0x1 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 CTRLB SPI Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only PLOADEN Slave Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 TXEN Transmitter Enable 16 1 DATA SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 DBGCTRL SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 INTENCLR SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTENSET SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 MB Master on Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave on Bus Interrupt Enable 1 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 DRE Data Register Empty 0 1 read-only MB Master on Bus 0 1 PREC Stop Received 0 1 RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave on Bus 1 1 TXC Transmit Complete 1 1 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x14 8 read-write n 0x0 0x0 ADDR Address 0 8 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xA 16 read-write n 0x0 0x0 BAUD Master Baud Rate 0 8 BAUDLOW Master Baud Rate Low 8 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-out 28 2 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 MB Master on Bus Interrupt Enable 0 1 SB Slave on Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 MB Master on Bus 0 1 SB Slave on Bus 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x14 32 read-write n 0x0 0x0 ADDR Address 1 7 ADDRMASK Address Mask 17 7 GENCEN General Call Address Enable 0 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUT SCL Low Time-out 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DIS Disabled 0x0 75 50-100 ns hold time 0x1 450 300-600 ns hold time 0x2 600 400-800 ns hold time 0x3 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x18 8 read-write n 0x0 0x0 DATA Data 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Ready Interrupt Enable 2 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 AMATCH Address Match 1 1 DRDY Data Ready 2 1 PREC Stop Received 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x10 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only LOWTOUT SCL Low Time-out 6 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x14 32 read-write n 0x0 0x0 ADDR Address 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xA 8 read-write n 0x0 0x0 BAUD Baud Register 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI SPI frame 0x0 SPI_ADDR SPI frame with address 0x2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK ADDRMASK is used as a mask to the ADDR register. 0x0 2ADDR The slave responds to the 2 unique addresses in ADDR and ADDRMASK. 0x1 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. 0x2 CHSIZE Character Size 0 3 PLOADEN Slave Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only TXC Transmit Complete 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SYNCBUSY Synchronization Busy 15 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud 0xA 16 read-write n 0x0 0x0 BAUD Baud Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect 0 USART frame 0x0 1 USART frame with parity 0x1 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run In Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM_PAD0 0x0 PAD1 SERCOM_PAD1 0x1 PAD2 SERCOM_PAD2 0x2 PAD3 SERCOM_PAD3 0x3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 1 TXPOSelect PAD0 TXD at PAD0, XCK at PAD1 0x0 PAD2 TXD at PAD2, XCK at PAD3 0x1 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x18 16 read-write n 0x0 0x0 DATA Data 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x8 8 read-write n 0x0 0x0 DBGSTOP Debug Stop Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 DRE Data Register Empty 0 1 read-only RXC Receive Complete 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete 1 1 SERCOM_USART - STATUS USART Mode - - USART Status 0x10 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 FERR Frame Error 1 1 PERR Parity Error 0 1 SYNCBUSY Synchronization Busy 15 1 read-only STATUS SPI Status 0x10 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read / Write Direction 3 1 read-only FERR Frame Error 1 1 LOWTOUT SCL Low Time-out 6 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SR Repeated Start 4 1 read-only SYNCBUSY Synchronization Busy 15 1 read-only SYSCTRL System Control SYSCTRL 0x0 0x0 0x2C registers n SYSCTRL 1 BOD33 3.3V Brown-Out Detector (BOD33) Control 0x34 32 read-write n 0x0 0x0 ACTION Action when Threshold Crossed 3 2 CEN Clock Enable 9 1 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 LEVEL Threshold Level 16 6 MODE Operation Modes 8 1 PSEL Prescaler Select 12 4 RUNSTDBY Run during Standby 6 1 DFLLCTRL DFLL Config 0x24 16 read-write n 0x0 0x0 CCDIS Chill Cycle Disable 8 1 ENABLE Enable 1 1 LLAW Lose Lock After Wake 4 1 MODE Mode Selection 2 1 ONDEMAND Enable on Demand 7 1 QLDIS Quick Lock Disable 9 1 RUNSTDBY Run during Standby 6 1 STABLE Stable Frequency 3 1 DFLLMUL DFLL Multiplier 0x2C 32 read-write n 0x0 0x0 CSTEP Maximum Coarse Step Size 26 6 FSTEP Maximum Fine Step Size 16 10 MUL Multiplication Value 0 16 DFLLSYNC DFLL Synchronization 0x30 8 read-write n 0x0 0x0 READREQ Read Request Synchronization 7 1 write-only DFLLVAL DFLL Calibration Value 0x28 32 read-write n 0x0 0x0 COARSE Coarse Calibration Value 10 6 DIFF Multiplication Ratio Difference 16 16 read-only FINE Fine Calibration Value 0 10 INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 B33SRDY BOD33 Synchronization Ready 11 1 BOD33DET BOD33 Detection 10 1 BOD33RDY BOD33 Ready 9 1 DFLLLCKC DFLL Lock Coarse 7 1 DFLLLCKF DFLL Lock Fine 6 1 DFLLOOB DFLL Out Of Bounds 5 1 DFLLRCS DFLL Reference Clock Stopped 8 1 DFLLRDY DFLL Ready 4 1 OSC32KRDY OSC32K Ready 2 1 OSC8MRDY OSC8M Ready 3 1 XOSC32KRDY XOSC32K Ready 1 1 XOSCRDY XOSC Ready 0 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 B33SRDY BOD33 Synchronization Ready 11 1 BOD33DET BOD33 Detection 10 1 BOD33RDY BOD33 Ready 9 1 DFLLLCKC DFLL Lock Coarse 7 1 DFLLLCKF DFLL Lock Fine 6 1 DFLLOOB DFLL Out Of Bounds 5 1 DFLLRCS DFLL Reference Clock Stopped 8 1 DFLLRDY DFLL Ready 4 1 OSC32KRDY OSC32K Ready 2 1 OSC8MRDY OSC8M Ready 3 1 XOSC32KRDY XOSC32K Ready 1 1 XOSCRDY XOSC Ready 0 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 B33SRDY BOD33 Synchronization Ready 11 1 BOD33DET BOD33 Detection 10 1 BOD33RDY BOD33 Ready 9 1 DFLLLCKC DFLL Lock Coarse 7 1 DFLLLCKF DFLL Lock Fine 6 1 DFLLOOB DFLL Out Of Bounds 5 1 DFLLRCS DFLL Reference Clock Stopped 8 1 DFLLRDY DFLL Ready 4 1 OSC32KRDY OSC32K Ready 2 1 OSC8MRDY OSC8M Ready 3 1 XOSC32KRDY XOSC32K Ready 1 1 XOSCRDY XOSC Ready 0 1 OSC32K OSC32K Control 0x18 32 read-write n 0x0 0x0 CALIB Calibration Value 16 7 EN1K 1kHz Output Enable 3 1 EN32K 32kHz Output Enable 2 1 ENABLE Enable 1 1 ONDEMAND Enable on Demand 7 1 RUNSTDBY Run during Standby 6 1 STARTUP Start-Up Time 8 3 WRTLOCK Write Lock 12 1 OSC8M OSC8M Control A 0x20 32 read-write n 0x0 0x0 CALIB Calibration Value 16 12 ENABLE Enable 1 1 FRANGE Frequency Range 30 2 ONDEMAND Enable on Demand 7 1 PRESC Prescaler Select 8 2 RUNSTDBY Run during Standby 6 1 OSCULP32K OSCULP32K Control 0x1C 8 read-write n 0x0 0x0 CALIB Calibration Value 0 5 WRTLOCK Write Lock 7 1 PCLKSR Power and Clocks Status 0xC 32 read-only n 0x0 0x0 B33SRDY BOD33 Synchronization Ready 11 1 read-only BOD33DET BOD33 Detection 10 1 read-only BOD33RDY BOD33 Ready 9 1 read-only DFLLLCKC DFLL Lock Coarse 7 1 read-only DFLLLCKF DFLL Lock Fine 6 1 read-only DFLLOOB DFLL Out Of Bounds 5 1 read-only DFLLRCS DFLL Reference Clock Stopped 8 1 read-only DFLLRDY DFLL Ready 4 1 read-only OSC32KRDY OSC32K Ready 2 1 read-only OSC8MRDY OSC8M Ready 3 1 read-only XOSC32KRDY XOSC32K Ready 1 1 read-only XOSCRDY XOSC Ready 0 1 read-only VREF VREF Control A 0x40 32 read-write n 0x0 0x0 BGOUTEN Bandgap Output Enable 2 1 CALIB Voltage Reference Calibration Value 16 11 TSEN Temperature Sensor Output Enable 1 1 VREG VREG Control 0x3C 16 read-write n 0x0 0x0 FORCELDO Force LDO Voltage Regulator 13 1 RUNSTDBY Run during Standby 6 1 XOSC XOSC Control 0x10 16 read-write n 0x0 0x0 AMPGC Automatic Amplitude Gain Control 11 1 ENABLE Enable 1 1 GAIN Gain Value 8 3 ONDEMAND Enable on Demand 7 1 RUNSTDBY Run during Standby 6 1 STARTUP Start-Up Time 12 4 XTALEN Crystal Oscillator Enable 2 1 XOSC32K XOSC32K Control 0x14 16 read-write n 0x0 0x0 AAMPEN Automatic Amplitude Control Enable 5 1 EN1K 1kHz Output Enable 4 1 EN32K 32kHz Output Enable 3 1 ENABLE Enable 1 1 ONDEMAND Enable on Demand 7 1 RUNSTDBY Run during Standby 6 1 STARTUP Start-Up Time 8 3 WRTLOCK Write Lock 12 1 XTALEN Crystal Oscillator Enable 2 1 TC0 Basic Timer Counter 0 TC 0x0 0x0 0x40 registers n TC0 13 CC0 COUNT16 Compare/Capture 0x18 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 CC1 COUNT16 Compare/Capture 0x1A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 COUNT COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC1 Basic Timer Counter 1 TC 0x0 0x0 0x40 registers n TC1 14 CC0 COUNT16 Compare/Capture 0x18 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 CC1 COUNT16 Compare/Capture 0x1A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 COUNT COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC2 Basic Timer Counter 2 TC 0x0 0x0 0x40 registers n TC2 15 CC0 COUNT16 Compare/Capture 0x18 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 CC1 COUNT16 Compare/Capture 0x1A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 COUNT COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC3 Basic Timer Counter 3 TC 0x0 0x0 0x40 registers n TC3 16 CC0 COUNT16 Compare/Capture 0x18 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 CC1 COUNT16 Compare/Capture 0x1A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 COUNT COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC4 Basic Timer Counter 4 TC 0x0 0x0 0x40 registers n TC4 17 CC0 COUNT16 Compare/Capture 0x18 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 CC1 COUNT16 Compare/Capture 0x1A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 COUNT COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC5 Basic Timer Counter 5 TC 0x0 0x0 0x40 registers n TC5 18 CC0 COUNT16 Compare/Capture 0x18 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 CC1 COUNT16 Compare/Capture 0x1A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 COUNT COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0x0 CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0x0 CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0x0 CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 GCLK_TC 0x0 DIV2 GCLK_TC/2 0x1 DIV4 GCLK_TC/4 0x2 DIV8 GCLK_TC/8 0x3 DIV16 GCLK_TC/16 0x4 DIV64 GCLK_TC/64 0x5 DIV256 GCLK_TC/256 0x6 DIV1024 GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset Counter on next GCLK 0x0 PRESC Reload or reset Counter on next prescaler clock 0x1 RESYNC Reload or reset Counter on next GCLK. Reset prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force start, restart or retrigger 0x1 STOP Force stop 0x2 DIR Counter Direction 0 1 ONESHOT One-shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0x0 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured into CC0 Pulse Width in CC1 0x5 PWP Period captured into CC1 Pulse Width on CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0x0 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x0 0x0 SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only WDT Watchdog Timer WDT 0x0 0x0 0x10 registers n WDT 2 CLEAR Clear 0x8 8 write-only n 0x0 0x0 CLEAR Watchdog Clear 0 8 write-only CLEARSelect KEY Clear Key 0xa5 CONFIG Configuration 0x1 8 read-write n 0x0 0x0 PER Time-Out Period 0 4 PERSelect 8 8 clock cycles 0x0 16 16 clock cycles 0x1 32 32 clock cycles 0x2 64 64 clock cycles 0x3 128 128 clock cycles 0x4 256 256 clock cycles 0x5 512 512 clock cycles 0x6 1K 1024 clock cycles 0x7 2K 2048 clock cycles 0x8 4K 4096 clock cycles 0x9 8K 8192 clock cycles 0xa 16K 16384 clock cycles 0xb WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect 8 8 clock cycles 0x0 16 16 clock cycles 0x1 32 32 clock cycles 0x2 64 64 clock cycles 0x3 128 128 clock cycles 0x4 256 256 clock cycles 0x5 512 512 clock cycles 0x6 1K 1024 clock cycles 0x7 2K 2048 clock cycles 0x8 4K 4096 clock cycles 0x9 8K 8192 clock cycles 0xa 16K 16384 clock cycles 0xb CTRL Control 0x0 8 read-write n 0x0 0x0 ALWAYSON Always-On 7 1 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 EWCTRL Early Warning Interrupt Control 0x2 8 read-write n 0x0 0x0 EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect 8 8 clock cycles 0x0 16 16 clock cycles 0x1 32 32 clock cycles 0x2 64 64 clock cycles 0x3 128 128 clock cycles 0x4 256 256 clock cycles 0x5 512 512 clock cycles 0x6 1K 1024 clock cycles 0x7 2K 2048 clock cycles 0x8 4K 4096 clock cycles 0x9 8K 8192 clock cycles 0xa 16K 16384 clock cycles 0xb INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EW Early Warning 0 1 STATUS Status 0x7 8 read-only n 0x0 0x0 SYNCBUSY Synchronization Busy 7 1 read-only